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CS43L43 Low Voltage, Stereo DAC with Headphone Amp
Features
l 16-Pin
Description
The CS43L43 is a complete stereo digital-to-analog output system including interpolation, 1-bit D/A conversion, analog filtering, volume control, and a headphone amplifier, in a 16-pin TSSOP package. The CS43L43 is based on delta-sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows infinite adjustment of the sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS43L43 contains on-chip digital bass and treble boost, peak signal limiting and de-emphasis. The CS43L43 operates from a +1.8 V to +3.3 V supply and consumes only 16 mW of power with a 1.8 V supply. These features are ideal for portable CD, MP3 and MD players and other portable playback systems that require extremely low power consumption.
TSSOP package l 1.8 to 3.3 Volt supply l 24-Bit conversion / 96 kHz sample rate l 94 dB dynamic range at 3 V supply l -85 dB THD+N at 1.8 V supply l Low power consumption l Digital volume control
--96 dB attenuation, 1 dB step size
l Digital
bass and treble boost
--Selectable corner frequencies --Up to 12 dB boost in 1 dB increments
l Peak
signal limiting to prevent clipping l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz l Headphone amplifier
--up to 25 mWrms power output into 16 load* --25 dB analog attenuation and mute --Zero crossing click free level transitions
l ATAPI
mixing functions
* 1 kHz sine wave at 3.3V supply
ORDERING INFORMATION CS43L43-KZ -10 to 70 C CDB43L43
16-pin TSSOP Evaluation Board
DIF1/SDA RST VA VL
DIF0/SCL
VQ_HP
VA_HP
CONTROL PORT
LRCK DEEMPHASIS
DIGITAL VOLUME CONTROL BASS/TREBLE BOOST LIMITING DIGITAL FILTERS
DAC
ANALOG FILTER
ANALOG VOLUME CONTROL HEADPHONE AMPLIFIER
HP_A
SCLK/DEM
SERIAL PORT
DAC
ANALOG FILTER
ANALOG VOLUME CONTROL
HP_B
SDATA
GND
MCLK
FILT+
REF_GND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
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TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................4 ANALOG CHARACTERISTICS..........................................................................4 POWER AND THERMAL CHARACTERISTICS ................................................6 DIGITAL CHARACTERISTICS...........................................................................7 ABSOLUTE MAXIMUM RATINGS .....................................................................7 RECOMMENDED OPERATING CONDITIONS .................................................7 SWITCHING CHARACTERISTICS ....................................................................8 SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE 10 2.0 TYPICAL CONNECTION DIAGRAM ...............................................................11 3.0 REGISTER QUICK REFERENCE .....................................................................12 4.0 REGISTER DESCRIPTION ...............................................................................13 4.1 Power and Muting Control (address 01h) .................................................13 4.2 Channel A Analog Attenuation Control (address 02h) (VOLA).................15 4.3 Channel B Analog Attenuation Control (address 03h) (VOLB).................15 4.4 Channel A Digital Volume Control (address 04h) (DVOLA) ......................15 4.5 Channel B Digital Volume Control (address 05h) (DVOLb).......................15 4.6 Tone Control (address 06h).......................................................................16 4.7 Mode Control (address 07h) ......................................................................17 4.8 Limiter Attack Rate (address 08h) (ARATE)..............................................18 4.9 Limiter Release Rate (address 09h) (RRATE) ......................................19 4.10 Volume and Mixing Control (address 0Ah) ..............................................19 4.11 Mode Control 2 (address 0Bh).................................................................21 5.0 PIN DESCRIPTION ............................................................................................22 6.0 APPLICATIONS .................................................................................................25 6.1 Grounding and Power Supply Decoupling ................................................25 6.2 Clock Modes .............................................................................................25 6.3 De-Emphasis ............................................................................................25 6.4 Recommended Power-up Sequence ........................................................25 6.5 Popguard(R) Transient Control ...................................................................25 7.0 CONTROL PORT INTERFACE .........................................................................26 7.1 Memory Address Pointer (MAP) .................................................................27 8.0 PARAMETER DEFINITIONS .............................................................................35 Total Harmonic Distortion + Noise (THD+N) ....................................................35 Dynamic Range ................................................................................................35
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Philips Semiconductors. PopGuard is a trademark , Crystal is a registered trademark of Cirrus Logic, Inc. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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Interchannel Isolation ....................................................................................... 35 Interchannel Gain Mismatch............................................................................. 35 Gain Error ......................................................................................................... 35 Gain Drift .......................................................................................................... 35 9.0 REFERENCES ................................................................................................... 35 10.0 PACKAGE DIMENSIONS ............................................................................... 36
LIST OF FIGURES
Figure 1. External Serial Mode Input Timing ..................................................................... 9 Figure 2. Internal Serial Mode Input Timing ...................................................................... 9 Figure 3. Internal Serial Clock Generation ........................................................................ 9 Figure 4. Control Port Timing - Two-Wire Mode .............................................................. 10 Figure 5. Typical Connection Diagram ............................................................................11 Figure 6. Control Port Timing, Two-Wire Mode ...............................................................27 Figure 7. Base-Rate Stopband Rejection ........................................................................ 28 Figure 8. Base-Rate Transition Band .............................................................................. 28 Figure 9. Base-Rate Transition Band (Detail) .................................................................. 28 Figure 10. Base-Rate Passband Ripple .......................................................................... 28 Figure 11. High-Rate Stopband Rejection ....................................................................... 28 Figure 12. High-Rate Transition Band ............................................................................. 28 Figure 13. High-Rate Transition Band (Detail) ................................................................ 29 Figure 14. High-Rate Passband Ripple ........................................................................... 29 Figure 15. Output Test Load ............................................................................................ 29 Figure 16. CS43L43 Control Port Mode - Serial Audio Format 0 (I2S) ............................ 30 Figure 17. CS43L43 Control Port Mode - Serial Audio Format 1 (I2S) ............................ 30 Figure 18. CS43L43 Control Port Mode - Serial Audio Format 2 .................................... 30 Figure 19. CS43L43 Control Port Mode - Serial Audio Format 3 .................................... 31 Figure 20. CS43L43 Control Port Mode - Serial Audio Format 4 .................................... 31 Figure 21. CS43L43 Control Port Mode - Serial Audio Format 5 .................................... 31 Figure 22. CS43L43 Control Port Mode - Serial Audio Format 6 .................................... 32 Figure 23. CS43L43 Stand-Alone Mode - Serial Audio Format 0 (I2S) ........................... 32 Figure 24. CS43L43 Stand-Alone Mode - Serial Audio Format 1 .................................... 32 Figure 25. CS43L43 Stand-Alone Mode - Serial Audio Format 2 .................................... 33 Figure 26. CS43L43 Stand-Alone Mode - Serial Audio Format 3 .................................... 33 Figure 27. De-Emphasis Curve ....................................................................................... 34 Figure 28. ATAPI Block Diagram ..................................................................................... 34
LIST OF TABLES
Table 1. Example Analog Volume Settings .....................................................................15 Table 2. Example Digital Volume Settings ...................................................................... 15 Table 3. Example Bass Boost Settings ........................................................................... 16 Table 4. Example Treble Boost Settings ......................................................................... 16 Table 5. Example Limiter Attack Rate Settings ...............................................................18 Table 6. Example Limiter Release Rate Settings ............................................................ 19 Table 7. ATAPI Decode ................................................................................................... 20 Table 8. Digital Interface Format ..................................................................................... 21 Table 9. Stand Alone De-Emphasis Control .................................................................... 23 Table 10. HRM Common Clock Frequencies .................................................................. 23 Table 11. BRM Common Clock Frequencies .................................................................. 23 Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) ...................... 23
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1.0 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; GND = 0 V; Logic "1" = VL = 1.8 V; Logic "0" =
GND = 0 V; Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz. Test load RL = 16 , CL = 10 pF (See Figure 15)) Base-rate Mode Parameter Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit (Note 1) unweighted A-Weighted unweighted A-Weighted (Note 1) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) (Note 1) unweighted A-Weighted unweighted A-Weighted (Note 1) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) Symbol Min Typ Max Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V TBD TBD 88 91 86 89 -82 -68 -28 -80 -66 -26 66 TBD TBD TBD 89 92 87 90 -85 -69 -29 -83 -67 -27 66 TBD dB dB dB dB dB dB dB dB dB dB dB High-Rate Mode Min Typ Max Unit
16-Bit
Interchannel Isolation Dynamic Range. 18 to 24-Bit. 16-Bit. Total Harmonic Distortion + Noise. 18 to 24-Bit.
Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V TBD TBD 91 93 89 91 -76 -71 -31 -78 -69 -29 66 TBD TBD TBD 92 94 90 92 -73 -72 -32 -78 -70 -30 66 TBD dB dB dB dB dB dB dB dB dB dB dB
16-Bit.
Interchannel Isolation.
Notes: 1. One-half LSB of triangular PDF dither is added to data.
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ANALOG CHARACTERISTICS (Continued)
Parameters Analog Output Full Scale Headphone Output Voltage Headphone Output Quiescent Voltage Interchannel Gain Mismatch Gain Drift Maximum Headphone Output AC-Current Symbol Min TBD Typ 0.55 x VA 0.5 x VA_HP 0.1 100 31 52 Max TBD Units Vpp VDC dB ppm/C mA mA
VQ_HP
VA=VA_HP=1.8V VA=VA_HP=3.0V
IHP
Base-rate Mode Parameter Passband (Note 3) to -0.05 dB corner to -0.1 dB corner to -3 dB corner Symbol Min Typ Max Combined Digital and On-chip Analog Filter Response (Note 2) 0 0 -.02 .5465 (Note 5) tgd 50 9/Fs 0.36/Fs .4535 .4998 +.08 +.2/-.1 +.05/-.14 +0/-.22
High-Rate Mode Min Typ Max Unit
0 0 0 .577 55 -
4/Fs 1.39/Fs 0.23/Fs (Note 6)
.4426 .4984 +0.11 -
Fs Fs Fs dB Fs dB s s s dB dB dB
Frequency Response 10 Hz to 20 kHz (Note 4) StopBand StopBand Attenuation Group Delay Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz
Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-14) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. Referenced to a 1 kHz, full-scale sine wave. 5. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 6. De-emphasis is not available in High-Rate Mode.
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POWER AND THERMAL CHARACTERISTICS GND = 0 V ( All voltages with respect to ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)
Base-rate Mode Parameters Power Supplies Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode (Note 7) Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode (Note 7) Total Power DissipationNormal Operation Max Headphone Power Dissipation With Full-scale Output and 16ohm Load Package Thermal Resistance Power Supply Rejection Ratio (Note 8) VA=1.8V VA_HP=1.8V VL=1.8V VA=1.8V VA_HP=1.8V VL=1.8V VA=3.0V VA_HP=3.0V VL=3.0V VA=3.0V VA_HP=3.0V VL=3.0V All Supplies=1.8V All Supplies=3.0V VA_HP=1.8V VA_HP=3.0V 1 kHz 60 Hz
JA PSRR
Symbol IA IA_HP ID_L IA IA_HP ID_L IA IA_HP ID_L IA IA_HP ID_L
Min -
Typ 7.3 1.5 4 TBD TBD TBD 10.5 1.5 9.3 TBD TBD TBD 16 36 TBD TBD 75 60 40
Max TBD TBD -
Units mA mA A A A A mA mA A A A A mW mW mW mW C/Watt dB dB
Notes: 7. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 8. Valid with the recommended capacitor values on FILT+ and VQ_HP as shown in Figure 5. Increasing the capacitance will also increase the PSRR. NOTE: Care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 A will cause degradation in analog performance.
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DIGITAL CHARACTERISTICS (TA = 25C; VL =
Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance VIL Iin 1.7V - 3.6V; GND = 0 V) Min 0.7 x VL Typ 8 Max 0.3 x VL 10 Units V V
A pF
Symbol VIH
ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)
Parameters DC Power Supplies: Positive Analog Headphone Digital I/O Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VA_HP VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -0.3 -55 -65 Max 4.0 4.0 4.0 10 VL + 0.4 125 150 Units V V V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters Ambient Temperature DC Power Supplies: Positive Analog Headphone Digital I/O Symbol TA VA VA_HP VL Min -10 1.7 0.9 1.7 Typ Max 70 3.6 3.6 3.6 Units C V V V
(Note 9)
9. To prevent clipping the outputs, VA_HPMIN is limited by the Full-Scale Output Voltage VFS_HP, where VA_HP must be 200 mV greater than VFS_HP. However, if distortion is not a concern, VA_HP may be as low as 0.9 V at any time.
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SWITCHING CHARACTERISTICS (TA = -10 to 70C; VA = 1.7V - 3.6V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20pF) Parameters Input Sample Rate MCLK Pulse Width High MCLK Pulse Width High MCLK Pulse Width High MCLK Pulse Width High MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width Low MCLK Pulse Width Low External SCLK Mode LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low SCLK Pulse Width High SCLK Period Base Rate Mode High Rate Mode SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) SCLK Period SCLK rising to LRCK edge SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time Base Rate Mode High Rate Mode (Note 10) tsclkw tsclkr tsdlrs tsdh tsdh 1 ---------------SCLK
Symbol Base Rate Mode High Rate Mode MCLK/LRCK = 1024 MCLK/LRCK = 1024 MCLK/LRCK = 768 MCLK/LRCK = 768 MCLK/LRCK = 512 MCLK/LRCK = 512 Fs Fs
Min 2 50 7 7 10 10 15 15 25 25 35 35 40
Typ 50 50 tsclkw ----------------2
Max 50 100 60 -
Units kHz kHz ns ns ns ns ns ns ns ns ns ns % ns ns ns ns ns ns ns ns % ns
s
MCLK Pulse Width High MCLK / LRCK = 384 or 192 MCLK / LRCK = 384 or 192 MCLK / LRCK = 256 or 128 MCLK Pulse Width High MCLK / LRCK = 256 or 128
tsclkl tsclkh tsclkw tsclkw tslrd tslrs tsdlrs tsdh
20 20
1 --------------------( 128 )Fs 1 -----------------( 64 )Fs
20 20 20 20
1 --------------------- + 10 ( 512 )Fs 1 --------------------- + 15 ( 512 )Fs 1 --------------------- + 15 ( 384 )Fs
-
ns ns ns
Notes: 10. In Internal SCLK Mode, the duty cycle must be 50% +/- 1/2 MCLK Period.
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LRCK t slrd t slrs t sclkl t sclkh
LRCK
t sclkr
SDATA
SCLK
t sclkw
t sdlrs SDATA t sdh
t sdlrs *INTERNAL SCLK
t sdh
Figure 1. External Serial Mode Input Timing
Figure 2. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS43L43.
LRCK
MCLK 1
*INTERNAL SCLK
N 2
N
SDATA
Figure 3. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS43L43. N equals MCLK divided by SCLK
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SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE
(TA = 25 C; VL = 1.7V - 3.6V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 30 pF) Parameter Two-Wire Mode (Note 11) SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time of SCL Rise Time SDA Fall Time of SDA Setup Time for Stop Condition (Note 12) fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc trd tfd tsusp 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 100 25 25 1 300 kHz ns s s s s s s ns ns ns s ns s Symbol Min Max Unit
Notes: 11. The Two-Wire Mode is compatible with the I2C protocol. 12. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
t rd
Stop t rd
t hdst
t high
t
hdst
t fc
t susp
t
low
t
hdd
t sud
t sust
t rc
Figure 4. Control Port Timing - Two-Wire Mode
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2.0 TYPICAL CONNECTION DIAGRAM
1.8 to 3.3 V Supply
*Ferrite bead + *1.0 F + 0.1 F 12 VA 4 0.1 F VL 0.1 F 13 VA_HP HP_A
*Ferrite bead *1.0 F
0.9 to 3.3 V Supply
1.8 to 3.3 V Supply
*Ferrite bead + *1.0 F
10 220 F + 1 K
47 H
16 Headphones
CS43L43
5 Digital Audio Source 1 3
2
MCLK LRCK SCLK/DEM
220 F HP_B 14 + 1 K
47 H
VQ_HP
7
SDATA
FILT+ c/ Mode Configuration 16 6 15 RST DIF0/SCL DIF1/SDA
REF_GND
8 + 1.0 F + 1.0 F
9
* Optional
GND
11
Figure 5. Typical Connection Diagram
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3.0 REGISTER QUICK REFERENCE
Addr
0h 1h
Function
Reserved default Power and Muting Control default Channel A Analog Attenuation Control default Channel B Analog Attenuation Control default Channel A Digital Volume Control default Channel B Digital Volume Control default Tone Control default Mode Control default Limiter Attack Rate default Limiter Release Rate default Volume and Mixing Control default Mode Control 2 default
7
Reserved 0 AMUTE 1 VOLA7 0 VOLB7 0 DVOLA7 0 DVOLB7 0 BB3 0 BBCF1 0 ARATE7 0 RRATE7 0 TC1 0 0
6
Reserved 0 SZC1 1 VOLA6 0 VOLB6 0 DVOLA6 0 DVOLB6 0 BB2 0 BBCF0 0 ARATE6 0 RRATE6 0 TC0 0 0
5
Reserved 0 SZC0
4
Reserved 0 POR 1 VOLA4 0 VOLB4 0 DVOLA4 0 DVOLB4 0 BB0 0 TBCF0 0 ARATE4 0 RRATE4 1 LIM_EN 0 Reserved 0
3
Reserved 0 Reserved 0 VOLA3 0 VOLB3 0 DVOLA3 0 DVOLB3 0 TB3 0 A=B 0 ARATE3 0 RRATE3 0 ATAPI3 1 Reserved 0
2
Reserved 0 Reserved 0 VOLA2 0 VOLB2 0 DVOLA2 0 DVOLB2 0 TB2 0 DEM1 0 ARATE2 0 RRATE2 0 ATAPI2 0 DIF2 0
1
Reserved 0 PDN 1 VOLA1 0 VOLB1 0 DVOLA1 0 DVOLB1 0 TB1 0 DEM0 0 ARATE1 0 RRATE1 0 ATAPI1 0 DIF1 0
0
Reserved 0 Reserved 0 VOLA0 0 VOLB0 0 DVOLA0 0 DVOLB0 0 TB0 0 VCBYP 0 ARATE0 0 RRATE0 0 ATAPI0 1 DIF0 0
0
VOLA5 0 VOLB5 0 DVOLA5 0 DVOLB5 0 BB1 0 TBCF1 0 ARATE5 1 RRATE5 0 TC_EN 0 Reserved 0
2h
3h
4h
5h
6h 7h 8h 9h Ah
Bh
MCLKDIV Reserved
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4.0 REGISTER DESCRIPTION
4.1 POWER AND MUTING CONTROL (ADDRESS 01H)
7 AMUTE 1 6 SZC1 1 5 SZC0 0 4 POR 1 3 RESERVED 0 2 RESERVED 0 1 PDN 1 0 RESERVED 0
4.1.1 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register. 4.1.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC) Default = 10 00 - Immediate Change 01 - Zero Cross Digital and Analog 10 - Ramped Digital and Analog 11 - Reserved Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Digital and Analog Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Ramped Digital and Analog Soft Ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Analog level changes will occur in 1 dB steps on a signal zero crossing. The analog level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
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4.1.3 POPGUARD(R) TRANSIENT CONTROL (POR) Default - 1 0 - Disabled 1 - Enabled Function: The Popguard(R) Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this feature is enabled. Please see section 6.5 for implementation details. 4.1.4 POWER DOWN (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state whenever this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation will begin.
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4.2 CHANNEL A ANALOG ATTENUATION CONTROL (ADDRESS 02H) (VOLA) 4.3 CHANNEL B ANALOG ATTENUATION CONTROL (ADDRESS 03H) (VOLB)
7 VOLx7 0 6 VOLx6 0 5 VOLx5 0 4 VOLx4 0 3 VOLx3 0 2 VOLx2 0 1 VOLx1 0 0 VOLx0 0
Default = 0 dB (No attenuation) Function: The Analog Attenuation Control operates independently from the Digital Volume Control. The Analog Attenuation Control registers allow the user to attenuate the headphone output signal in 1 dB increments from 0 to -25 dB, using the analog volume control. Attenuation settings are decoded as shown in Table 1, using a 2's complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings greater than zero are interpreted as zero.
Binary Code 00000000 11110110 11110001 Decimal Value 0 -10 -15 Volume Setting 0 dB -10 dB -15 dB
Table 1. Example Analog Volume Settings 4.4 CHANNEL A DIGITAL VOLUME CONTROL (ADDRESS 04H) (DVOLA) 4.5 CHANNEL B DIGITAL VOLUME CONTROL (ADDRESS 05H) (DVOLB)
7 DVOLx7 0 6 DVOLx6 0 5 DVOLx5 0 4 DVOLx4 0 3 DVOLx3 0 2 DVOLx2 0 1 DVOLx1 0 0 DVOLx0 0
Default = 0 dB (No attenuation) Function: The Digital Volume Control allows the user to alter the signal level in 1 dB increments from +18 to -96 dB, using the Digital Volume Control. Volume settings are decoded as shown in Table 2, using a 2's complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. All volume settings less than - 96 dB are equivalent to muting the channel via the ATAPI bits (See Section 4.10.4). NOTES: Setting this register to values greater than +18 dB will cause distortion in the audio outputs.
Binary Code 00001010 00000111 00000000 11000100 10100110 Decimal Value 12 7 0 -60 -90 Volume Setting +12 dB +7 dB 0 dB -60 dB -90 dB
Table 2. Example Digital Volume Settings
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4.6 TONE CONTROL (ADDRESS 06H)
7 BB3 0 6 BB2 0 5 BB1 0 4 BB0 0 3 TB3 0 2 TB2 0 1 TB1 0 0 TB0 0
4.6.1 BASS BOOST LEVEL (BB) Default = 0 dB (No Bass Boost) Function: The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above +12 dB are interpreted as +12 dB.
Binary Code 0000 0010 1010 1001 1100
Decimal Value 0 2 6 9 12
Boost Setting 0 dB +2 dB +6 dB +9 dB +12 dB
Table 3. Example Bass Boost Settings 4.6.2 TREBLE BOOST LEVEL (TB) Default = 0 dB (No Treble Boost) Function: The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above +12 dB are interpreted as +12 dB. NOTE: Treble Boost is not available in High-Rate Mode.
Binary Code 0000 0010 1010 1001 1100 Decimal Value 0 2 6 9 12 Boost Setting 0 dB +2 dB +6 dB +9 dB +12 dB
Table 4. Example Treble Boost Settings
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4.7 MODE CONTROL (ADDRESS 07H)
7 BBCF1 0 6 BBCF0 0 5 TBCF1 0 4 TBCF0 0 3 A=B 0 2 DEM1 0 1 DEM0 0 0 VCBYP 0
4.7.1 BASS BOOST CORNER FREQUENCY (BBCF) Default = 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - Reserved Function: The bass boost corner frequency is user selectable as shown above. 4.7.2 TREBLE BOOST CORNER FREQUENCY (TBCF) Default = 00 00 - 2 kHz 01 - 4 kHz 10 - 7 kHz 11 - Reserved Function: The treble boost corner frequency is user selectable as shown above. NOTE: Treble Boost is not available in High-Rate Mode. 4.7.3 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B) Default = 0 0 - Disabled 1 - Enabled Function: The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the A Channel Attenuation and Volume Control Bytes and the B Channel Bytes are ignored when this function is enabled. 4.7.4 DE-EMPHASIS CONTROL (DEM) Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (See Figure 27) NOTE: De-emphasis is not available in High-Rate Mode. DS479PP1 17
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4.7.5 DIGITAL VOLUME CONTROL BYPASS (VCBYP) Default = 0 0 - Disabled 1 - Enabled Function: When this function is enabled the digital volume control section is bypassed. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog attenuation control will remain functional. 4.8 LIMITER ATTACK RATE (ADDRESS 08H) (ARATE)
7 ARATE7 0 6 ARATE6 0 5 ARATE5 1 4 ARATE4 0 3 ARATE3 0 2 ARATE2 0 1 ARATE1 0 0 ARATE0 0
Default = 20h - 1 LRCK's per 1/8 dB Function: The limiter attack rate is user selectable. The rate is a function of sampling frequency, Fs, and the value in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}. Where {value} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK's per 1/8 dB of change. NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Section 4.10.3).
Binary Code 00000001 00010100 00101000 00111100 01011010 Decimal Value 1 20 40 60 90 LRCK's per 1/8 dB 32 1.6 0.8 0.53 0.356
Table 5. Example Limiter Attack Rate Settings
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4.9 LIMITER RELEASE RATE (ADDRESS 09H) (RRATE)
7 RRATE7 0 6 RRATE6 0 5 RRATE5 0 4 RRATE4 1 3 RRATE3 0 2 RRATE2 0 1 RRATE1 0 0 RRATE0 0
Default = 10h - 32 LRCK's per 1/8 dB Function: The limiter release rate is user selectable. The rate is a function of sampling frequency, Fs, and the value in Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}. Where {value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK's per 1/8 dB of change. NOTE: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Section 4.10.3).
Binary Code 00000001 00010100 00101000 00111100 01011010 Decimal Value 1 20 40 60 90 LRCK's per 1/8 dB 512 25 12 8 5
Table 6. Example Limiter Release Rate Settings 4.10 VOLUME AND MIXING CONTROL (ADDRESS 0AH)
7 TC1 0 6 TC0 0 5 TC_EN 0 4 LIM_EN 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1
4.10.1 TONE CONTROL MODE (TC) Default = 00 00 - All settings are taken from user registers 01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz 10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz 11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz Function: The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured. The user defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used when these bits are set to `00'. Alternately, one of three pre-defined settings may be used. 4.10.2 TONE CONTROL ENABLE (TC_EN) Default = 0 0 - Disabled 1 - Enabled Function: The Bass Boost and Treble Boost features are active when this function is enabled.
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4.10.3 PEAK SIGNAL LIMITER ENABLE (LIM_EN) Default = 0 0 - Disabled 1 - Enabled Function: The CS43L43 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is still clipping, then the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate register. Once the signal has dropped below the clipping level, the attenuation is decreased back to the user selected level and then, the Bass Boost is increased back to the user selected level. The release rate is determined by the Limiter Release Rate register. NOTE: The A=B bit should be set to `1' for optimal limiter performance. 4.10.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI) Default = 1001 - HP_A = L, HP_B = R (Stereo) Function: The CS43L43 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 7 and Figure 28 for additional information. NOTE: All mixing functions occur prior to the digital volume control.
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HP_A MUTE MUTE MUTE MUTE R R R R L L L L [(L+R)/2] [(L+R)/2] [(L+R)/2] [(L+R)/2] HP_B MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2]
Table 7. ATAPI Decode
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4.11 MODE CONTROL 2 (ADDRESS 0BH)
7 MCLKDIV 0 6 RESERVED 0 5 RESERVED 0 4 RESERVED 0 3 RESERVED 0 2 DIF2 0 1 DIF1 0 0 DIF0 0
4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. NOTE: Internal SCLK is not available when this function is enabled. 4.11.2 DIGITAL INTERFACE FORMAT (DIF) Default = 000 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SLCK) Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 16-22. NOTE: Internal SCLK is not available when MCLKDIV is enabled.
DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION I2S, up to 24-bit data, 64 x Fs Internal SLCK I2S, up to 24-bit data, 32 x Fs Internal SLCK Left Justified, up to 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 Format 0 1 2 3 4 5 6 1 FIGURE 16 17 18 19 20 21 22 17
Table 8. Digital Interface Format
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5.0 PIN DESCRIPTION
Left/Right Clock Serial Data Serial Clock/DEM Interface Power Master Clock DIF0/SCL HP Quiescent Voltage Reference Ground LRCK SDATA SCLK/DEM VL MCLK DIF0/SCL VQ_HP REF_GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RST DIF1/SDA HP_B VA_HP VA GND HP_A FILT+ Reset DIF1/SDA Headphone Output B Headphone Amp Power Analog Power Ground Headphone Output A Positive Voltage Reference
LRCK
1
Left/Right Clock (Input) - The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 16-26. Serial Audio Data (Input) - Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 16-26. Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control 2 (0Bh) register when in Control Port Mode or by the DIF1-0 pins when in Stand-Alone mode. The options are detailed in Figures 16-26. The CS3L43 supports both internal and external serial clock generation modes. The Internal Serial Clock Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode is always preferred. Internal Serial Clock Mode - In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon the Mode Control 2 (0Bh) register when in Control Port Mode or the DIF1-0 pins when in Stand-Alone mode as shown in Figures 16-26. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. External Serial Clock Mode - The CS3L43 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
SDATA
2
SCLK
3
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DEM 3 De-emphasis Control (Input) - When using Internal Serial Clock Mode, Pin 3 is available for de-emphasis control and selects the 44.1 kHz de-emphasis filter, see Table 9 and Figure 30. When using External Serial Clock Mode, de-emphasis control is not available.NOTE: De-emphasis is not available in High-Rate Mode. External DESCRIPTION
DEMO
0 Disabled 1 44.1 kHz Table 9. Stand Alone De-Emphasis Control
VL MCLK 4 5 Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC. Master Clock (Input) - The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note that some multiplication factors require setting the MCLKDIV bit (see Section 4.11.1). Tables 10 and 11 illustrates several standard audio sample rates and the required master clock frequencies. MCLK (MHz) HRM 192x 256x* 6.1440 8.1920 8.4672 11.2896 9.2160 12.2880 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760
Sample Rate (kHz) 32 44.1 48 64 88.2 96
128x 4.0960 5.6448 6.1440 8.1920 11.2896 12.2880
384x* 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh). Table 10. HRM Common Clock Frequencies Sample Rate (kHz) 32 44.1 48 MCLK (MHz) BRM 512x 16.3840 22.5792 24.5760
256x 8.1920 11.2896 12.2880
384x 12.2880 16.9344 18.4320
768x* 24.5760 32.7680 36.8640
1024x* 32.7680 45.1584 49.1520
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh). Table 11. BRM Common Clock Frequencies DIF0 and DIF1 (Stand-Alone Mode) 6 & 15 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 23-26
.
DIF1 0 0 1 1
DIF0 0 1 0 1
DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data
FORMAT 0 1 2 3
FIGURE 23 24 25 26
Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) SCL (Control Port Mode) 6 Serial Control Interface Clock (Input) - Clocks the serial control data into or out of SDA/CDIN.
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VQ_HP 7 Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp quiescent reference voltage. A capacitor must be connected from VQ_HP to analog ground, as shown in Figure 5. VQ_HP is not intended to supply external current. VQ_HP has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Reference Ground (Input) - Ground reference for the internal sampling circuits. Must be connected to analog ground. Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to analog ground, as shown in Figure 5. The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance.
REF_GND FILT+
8 9
HP_A and HP_B GND VA VA_HP SDA (Control Port Mode) RST
10 & 14 Headphone Outputs (Output) - The full scale analog headphone output level is specified in the Analog Characteristics specifications table. 11 12 13 15 16 Ground (Input) - Ground Reference. Analog Power (Input) - Analog power supply. Typically 1.8 to 3.3 VDC. Headphone Amp Power (Input) - Headphone amplifier power supply. Typically 0.9 to 3.3 VDC. Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. See "Recommended Power-up Sequence" on page 25.
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6.0 APPLICATIONS 6.1 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS43L43 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 5 shows the recommended power arrangement with VA, VA_HP and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin. completion of the Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. The desired register settings can be loaded while keeping the PDN bit set to 1. 3. If Control Port Mode is selected via the CP_EN bit, set the PDN bit to 0 which will initiate the power-up sequence, which requires approximately 50 S when the POR bit is set to 0. If the POR bit is set to 1, see Section 6.5 for total power-up timing.
6.5 Popguard(R) Transient Control
The CS43L43 uses Popguard(R) technology to minimize the effects of output transients during power-up and power-down. This technique minimizes the audio transients commonly produced by single-ended, single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is initially powered-up, the audio outputs, HP_A and HP_B, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach VQ_HP and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. To prevent transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from HP_A and HP_B. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
6.2 Clock Modes
The CS43L43 operates in one of two clocking modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz, see Table 10 and 11. All clock modes use 64x oversampling.
6.3 De-Emphasis
The CS43L43 includes on-chip digital de-emphasis. Figure 27 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
6.4 Recommended Power-up Sequence
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ_HP will remain low. 2. Bring RST high. The device will remain in a low power state with VQ_HP low and will initiate the Stand-Alone power-up sequence. The control port will be accessible at this time. If Control Port operation is desired, write the CP_EN bit prior to the
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To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 F capacitor and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds. Use of the Mute Control function on the line outputs is recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios. which are only limited by the external mute circuit. See the CDB43L43 datasheet for a suggested mute circuit
7.0 CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. In Control Port Mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 4. The 7-bit address field must be 0010000. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. The CS43L43 has MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. The Two-Wire control port mode is compatible with the I2C protocol.
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7.1 MEMORY ADDRESS POINTER (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
7.1.1 INCR (AUTO MAP INCREMENT ENABLE) Default = `0' 0 - Disabled 1 - Enabled 7.1.2 MAP0-3 (MEMORY ADDRESS POINTER) Default = `0000'
Note 1 SDA
001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL Start Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 6. Control Port Timing, Two-Wire Mode
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Figure 7. Base-Rate Stopband Rejection
Figure 8. Base-Rate Transition Band
Figure 9. Base-Rate Transition Band (Detail)
0 -10
-20
0 -10 -20 -30
Figure 10. Base-Rate Passband Ripple
-30 Amplitude dB
Amplitude dB
-40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-40 -50 -60 -70 -80 -90
-100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 11. High-Rate Stopband Rejection
Figure 12. High-Rate Transition Band
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0 -1 -2 -3 Amplitude dB
Amplitude dB 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15
-4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
-0.20 -0.25 -0.30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 13. High-Rate Transition Band (Detail)
Figure 14. High-Rate Passband Ripple
220 F HP_x + V out R L C L
GND
Figure 15. Output Test Load
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LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
External SCLK Mode
I2S, Up to 24-Bit data and INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 I2S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 16. CS43L43 Control Port Mode - Serial Audio Format 0 (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
External SCLK Mode
16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 I2S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2S,
up to 24-Bit Data Data Valid on Rising Edge of SCLK
I2S,
Figure 17. CS43L43 Control Port Mode - Serial Audio Format 1 (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 18. CS43L43 Control Port Mode - Serial Audio Format 2
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LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 19. CS43L43 Control Port Mode - Serial Audio Format 3
LRCK
Left Channel
Right Channel
SCLK
SDATA
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 20-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 20-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 40 Cycles per LRCK Period
Figure 20. CS43L43 Control Port Mode - Serial Audio Format 4
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 21. CS43L43 Control Port Mode - Serial Audio Format 5
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LRCK
Left Channel
Right Channel
SCLK
SDATA
10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 18-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 22. CS43L43 Control Port Mode - Serial Audio Format 6
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode I2 S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 I2S, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 I2
External SCLK Mode S, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 23. CS43L43 Stand-Alone Mode - Serial Audio Format 0 (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 24. CS43L43 Stand-Alone Mode - Serial Audio Format 1
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LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Internal SCLK Mode Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 25. CS43L43 Stand-Alone Mode - Serial Audio Format 2
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 26. CS43L43 Stand-Alone Mode - Serial Audio Format 3
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Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 27. De-Emphasis Curve
Left Channel Audio Data
Channel A Digital Volume Control
EQ
Analog Volume Control
MUTE
HP_A
Right Channel Audio Data
Channel B Digital Volume Control
EQ
Analog Volume Control
MUTE
HP_B
Figure 28. ATAPI Block Diagram
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CS43L43
8.0 PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
9.0 REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4343 Evaluation Board Datasheet 3) "The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
DS479PP1
35
CS43L43
10.0 PACKAGE DIMENSIONS
16L SSOP PACKAGE DRAWING
N
D
E1 A2 A1
L
E
A
e b SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.033 0.008 --0.169 -0.020 0 NOM --0.035 -0.197 0.252 0.173 0.026 0.024 -MAX 0.043 0.006 0.037 0.012 --0.177 -0.028 8 MIN -0.05 0.85 0.19 --4.30 -0.50 0
MILLIMETERS NOM --0.90 -5.00 6.40 4.40 0.65 0.60 -MAX 1.10 0.15 0.95 0.30 --4.50 -0.70 8
NOTE
2,3 1 1
JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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DS479PP1
* Notes *

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